1. Field of the Invention
The present invention relates to a decoding circuit, and more specifically a decoding circuit for use in a semiconductor read only memory.
2. Description of Related Art
Referring to FIGS. 1A and 1B, which are an equivalent circuit and a partial layout pattern of a conventional semiconductor read only memory, it has an NAND type cell structure in which "n" memory cells are connected in series in a column direction. According to one typical programming method, data is written by means of an ion implantation to selectively form depletion transistors "Dji" indicative of data "0" and enhancement transistors "Ejn" representative of data "1".
Now, assuming that the data has been written in the above mentioned programming manner, a method for reading data will be described.
A gate of a memory cell to be selected is brought to a low level by one of outputs X1 to Xn of a word selecting circuit, and on the other hand, a gate voltage of memory cells not to be selected is brought to a high level by the others outputs of the word selecting circuit. Assuming that the memory cell to be selected is the enhancement transistors "Ejn", since the gate voltage of the transistor of the memory cell to be selected is at the low level, the memory cell transistor to be selected is in an OFF condition, and therefore, no current flows through an NAND type cell column Yj composed of the series-connected "n" memory cells including the memory cell to be selected. On the other hand, assuming that the memory cell to be selected is the depletion transistors "Dji", since the gate voltage of the transistor of the memory cell to be selected is at the low level, the memory cell transistor to be selected is in an ON condition, and therefore, a current flows through the NAND type cell column Yj composed of the series-connected "n" memory cells including the memory cell to be selected. Therefore, by sensing this current, it is possible to read out the written data.
With a demand for a large scaling, the memory cells are being microminiaturized, and the gate oxide film are correspondingly being thinned. Therefore, since non-selected word lines have to be brought at the high level in a standby condition and in a normal reading condition, a a gate oxide film destruction has often occurred so that it becomes impossible to read the data from the memory cell, or a leakage current in the standby condition has increased.
Under this circumstance, Japanese Patent Application Laid-open Publication Heisei 4-095298 has proposed a decoding circuit so configured that a group of NAND type cells including a memory cell to be selected is divided into a plurality of cell blocks, and all non-selected word lines of one cell block including the memory cell to be selected are brought to the high level, but the words lines of the other cell blocks are maintained at a low level. In this proposed decoding circuit, however, when the selected block and the non-selected block are switched into a non-selected condition and in a selected condition, respectively, a parasitic capacitance of the word lines (gate capacitance of the memory cells) is charged or discharged at a time, so that noise occurs in power supply lines due to a charge current for charging the parasitic capacitance, and also, noise occurs in ground lines due to a discharge current for discharging the parasitic capacitance. These noises deteriorates characteristics of the decoding circuit itself, and gives an adverse influence on other circuits such as sense amplifiers through the power supply lines and the ground lines, with the result that the reading speed is deteriorated.
In order to overcome this defect, Japanese Patent Application Laid-open Publication Heisei 5-347094 (the disclosure of which is incorporated by reference in its entirety into the present application) has proposed another decoding circuit, which is shown in FIG. 2. In the shown decoding circuit, a word line driving circuit is composed of a predecoding unit 18 and a plurality of decoder blocks 191, 192, . . . , 19j which are provided in accordance with the number of memory cells and each of which includes a selecting unit 16 and a plurality of decoding units 171, 172, . . . , 17n provided for word lines X11, X12, . . . , X1n, respectively.
The predecoding unit 18 is configured to decode an external address signals A, B, C and D for generating signals XP1T to XPnT and XP1B to XPnB.
In the decoder block 191, the decoding unit 171 includes a P-channel MOS transistor (called a "PMOS transistor" hereinafter) P11, and a pair of N-channel MOS transistors (called a "NMOS transistor" hereinafter) N11 and N12 having their drain connected in common to a drain of the PMOS transistor P11 and their source connected to ground, the common-connected drains of the PMOS transistors P11 and the NMOS transistors N11 and N12 constituting an output node connected to the word line X11, and a gate of the NMOS transistors N11 and N12 being connected to receive a signal S1 outputted from the selecting unit 16.
The decoding units 171 to 17n have the same circuit construction, and the PMOS transistor P11 corresponds to PMOS transistors P21 to Pn1, and the NMOS transistor N11 corresponds to NMOS transistors N21 to Nn1. In addition, the NMOS transistor N12 corresponds to NMOS transistors N22 to Nn2, and the output node (word line) X11 corresponds to output nodes (word lines) X12 to X1n. Further explanation of the decoding units 171 to 17n will be omitted for simplification of the description.
Sources of the PMOS transistors P11 to Pn1 are connected to receive the signals signals XP1B to XPnB generated by the predecoding unit 18, respectively. Gates of the NMOS transistors are connected to receive the signals signals XP1T to XPnT generated by the predecoding unit 18, respectively.
Furthermore, the decoder blocks 191 to 19n have the same circuit construction, and therefore, explanation of the internal structure of the decoder blocks 192 to 19n will be omitted for simplification of the description. Selection signals E, F and G are supplied to the selecting unit 16 of each of the decoder blocks 191 to 19n. The output signals (word lines) X11 to X1n correspond to output signals (word lines) X21 to X2n of the decoder blocks 192, . . . , output signals Xj1 to Xjn of the decoder blocks 19j.
Here, it is assumed that, when the output signals XP2T and XP2B of the predecoding unit 18 are activated in response to the external address signal A, B, C and D, the output signal XP2T is brought to a high level, and the output signals XP2B is brought to a low Level. All of the other output signals XP1T, XP3T to XPnT are brought to the low level, and all of the other output signals XP1B, XP3B to XPnB are brought to the high level. In addition, in response to the external address signal E, F and G, the selecting unit 16 generates the active signal S1 of the low level.
In this situation, in the decoding unit 171, the PMOS transistor P11 and the NMOS transistor N12 receiving the output signal XP2T at its gate are turned on the word line X11 is pulled down to the low level.
In the other decoding units 172, 173, . . . , 17n, the corresponding NMOS transistors N22, N32, . . . , Nn2 are off, the corresponding transistors P21, P31, . . . , Pn1 are on. Accordingly, the word lines X12, X13, . . . , X1n are supplied with the high level from the corresponding outputs of the predecoding units 18, and therefore, are pulled up to the high level.
Thereafter, if the decoder block 191 becomes non-selected in response to the external address signal E, F and G, the selecting unit 16 generates the inactive signal S1 of the high level, which are supplied to the gate of the transistors P1 and N11, P21 and N21, . . . , Pn1 and Nn1, so that the PMOS transistors P11 to Pn1 are rendered off and the NMOS transistors N11 to Nn1 are rendered on. Accordingly, all the word lines X11 to X1n are pulled down to the low level. At this time, the circuit is so configured that the block select NMOS transistors N11 to Nn1 have a driving capability smaller than that of the transistors N12 to Nn2, so that the discharge speed is low.
As seen from the above, the conventional decoding circuit is such that the power supply potential of the decoding units is supplied from the predecoding unit so that the power supply noise is reduced by the on-resistance of the transistors in the predecoding unit, and in addition, the block select transistors are provided so as to lower the discharge speed so that the ground noise is also reduced.
Referring to FIG. 3, there is shown a layout pattern illustrating a portion of the decoding unit in the conventional decoding circuit. In the shown layout pattern, hatched elongated regions designate an aluminum wiring conductor, and pear-skin regions designate a polysilicon wiring conductor. In addition, rectangular regions surrounded by a thick solid line designate a diffused layer, and a rectangular region surrounded by a dotted line designates an N-well. Black squares show a contact hole.
In the shown layout pattern, thus, the polysilicon crossing the diffused layer constitutes a gate electrode, and a portion of the diffused layer at one side of this polysilicon forms a drain region, and a portion of the diffused layer at the other side of this polysilicon forms a source region. Accordingly, the NMOS transistors N11 and N12 and N21 and N22 are formed, and in addition, the PMOS transistors P11 and P21 are formed in the N-well. Thus, the decoding units 171 and 172 are constituted.
Here, it is also assumed that the circuit is designed on the basis of such a rule that the aluminum wiring conductor having a width of 1 .mu.m and the spacing between adjacent aluminum wiring conductors is 1 .mu.m. In addition, the transistor is so sized as to have a channel width of 6 .mu.m and a channel length of 1 .mu.m. In this case, a block including the decoding circuits 171 and 172 has a width X of 17 .mu.m and a length Y of 41 .mu.m.
Recently, there is a large demand for increasing a memory capacity and a reading speed in this type semiconductor memory, and also such memories are desired to be inexpensively available. In particular, in speeding up the semiconductor memory, the delay in the charge/discharge of the word lines, namely, the delay of the word selection signal, is a problem. In this connection, it might be considered to suppress the delay of the word selection signal by use of a multilayer wiring technique. However, this is expensive and results in an increased number of manufacturing steps. Accordingly, a product cost increases, and delivery of finished products is delayed.
If the multilayer wiring technique is not used, the wiring length becomes long. Therefore, in order to realized a high speed operation by solving the delay of the word selection signal, it is necessary to provide a plurality of word line driving circuits so as to reduce the parasitic capacitance and a parasitic resistance distributed on the word selection signal lines. However, if a plurality of word line driving circuits are provided, the area occupied by the word line driving circuits increases, in particular in the X direction.
Here, referring to the layout pattern of FIG. 3, in order to realize the conventional decoding unit, at least one ground aluminum wiring conductor and four aluminum wiring conductors for the signals from the predecoding unit are required. Assuming that the length of a memory cell block is equal to Y (41 .mu.m in the shown example), in order to locate the decoding units so that "n" signal lines corresponding to all the word selection signals are arranged within the range of this length Y, the decoding units have to be located continuously in the X direction.
Therefore, according to the layout pattern shown in FIG. 3, the two decoding units take 17 .mu.m in the X direction, and therefore, in order to realize the decoder block 191 shown in FIG. 2, the required size in the X direction becomes 17 .mu.m.times.n/2.
In the conventional product, the rate "Xs" in area of a unitary word driving circuit to the whole of a chip is about 10%. Accordingly, if the number "p" of unitary word driving circuits provided is 4, since the total area of all the unitary word driving circuits increases with the proportion of Xs.times.p=Xs.times.4=40%, the whole area of each chip becomes 1.4 times.
Accordingly, since the conventional decoding circuit as mentioned above has a large number of signal wiring conductors extending from the predecoding unit, the required chip area greatly depends upon the numbers of the aluminum wiring conductors used as the signal wirings. As a result, the chip area has inevitably increased.